In broadband signal switching equipment having a cross point matrix in FET technology whose switch elements respectively controlled by a holding memory cell are respectively formed by a series circuit of a switching transistor and of an input transistor, an n-channel series pass transistor that has its control electrode connected to a reference potential source is respectively inserted between the matrix output line and the following output amplifier circuit. This n-channel series pass transistor, together with a matrix output line pre-charging transistor connected to the input of the output amplifier circuit, forms a charge transfer circuit that effects a voltage amplification. A pre-charging transistor that also has its control electrode connected to the pre-charging phase/evaluation phase clock signal line is also connected to the input of an input driver circuit that precedes a matrix input line, a transfer gate that precedes the input driver circuit also being simultaneously controlled proceeding from this pre-charging phase/evaluation phase clock signal line.

A field programmable gate array includes a logic blocks, switching elements for establishing a signal propagation path, and memory cells provided corresponding to the switching elements for storing data determining on and off states of corresponding switching elements. In this gate array, a supply voltage fed to a power input terminal is transmitted to power supply nodes of logic circuit blocks. A booster circuit boosts the supply voltage fed to the power input terminal and feeds the boosted voltage to power supply nodes of memory cells for programming a signal propagation path. A high-level signal potential of each memory cell is fed to the gate of an n-channel MOS transistor which functions as the switching element. The switching elements are disposed on signal lines and serve to interconnect the signal lines selectively to establish a signal propagation path. The current supply capability of the MOS transistors is enhanced to realize faster propagation of the signal, and any harmful influence of the threshold voltage exerted on the signal amplitude loss can be suppressed by a rise of the gate potential in each MOS transistor.

A first user re-programmable interconnect architecture is provided wherein N switching elements are connected between selected interconnect conductors. The switching elements are controlled by M active storage elements, where M<N. A group of N switching elements are controlled by a group of M active storage elements, where M<N. The states of the M active storage elements are collectively decoded to identify the one of N switching elements to be turned on. A second user re-programmable interconnect architecture is provided wherein a group of N switching elements are connected between selected interconnect conductors and are partially selected by decoding the states of m.sub.1 active storage elements. The group of N switching elements are also partially selected by decoding the states of m.sub.2 active storage elements. The decoding is arranged such that t the states of m.sub.1 and m.sub.2 active storage elements each are decoded to provide a partial address to identify one of the N switching elements to be turned to its "on" state. The sum of m.sub.1 and m.sub.2 is less than N.

A first user re-programmable interconnect architecture is provided wherein N switching elements are connected between selected interconnect conductors. The switching elements are controlled by M active storage elements, where M<N. A group of N switching elements are controlled by a group of M active storage elements, where M<N. The states of the M active storage elements are collectively decoded to identify the one of N switching elements to be turned on. A second user re-programmable interconnect architecture is provided wherein a group of N switching elements are connected between selected interconnect conductors and are partially selected by decoding the states of m.sub.1 active storage elements. The group of N switching elements are also partially selected by decoding the states of m.sub.2 active storage elements. The decoding is arranged such that the states of m.sub.1 and m.sub.2 active storage elements each are decoded to provide a partial address to identify one of the N switching elements to be turned to its "on" state. The sum of m.sub.1 and m.sub.2 is less than N. Decoder lines in non-parallel relationship with the interconnect conductors provide increased routability. Partial depopulation of the matrices containing the switching elements provides added routability.