The invention relates to a channelizer or apparatus for sorting articles such as prepacked foodstuffs into channels each characterized by an individual weight band. The apparatus of the invention includes a weighting unit that weighs each article and produces information significant of the article weight that is transferred step by step through a train of preset registers storing channel weight band information until the transferred information agrees with the stored information. This agreement ...

A plurality of devices any one of which can request service by a central controlling unit are interconnected in a loop arrangement by an enabling line. The controlling unit is effectively coupled in parallel to all the devices so that the presence of a service request by one of them will immediately initiate operations that will result in one of the devices being granted service. Each device includes logic circuitry to force it to actuate its leg of the enabling line loop if it was the device gr...

An input/output bus for a data processing system which has extended addressing capabilities and a variable length handshake which accommodates the difference delays associated with various sets of logic and a two part address field which allows a bus unit and channel to be identified. The various units can disconnect from the bus during internal processing to free the bus for other activity. The unit removes the busy signal prior to dropping the data lines to allow a bus arbitration sequence to ...

A network consists of a programmable controller coupled to several sensors by an interface circuit. A common communication protocol is used to exchange messages containing commands and data between the devices coupled to the network. A protocol message packet has a header with fields for a task command, sensor identification, device status information and error codes. The header contains the same fields whether the message packet is for the interface circuit or one of the sensors connected to it...

A data processing system includes a plurality of data handling subsystems which communicate with each other by means of an interval transfer bus. The subsystems are located at ports along the bus and each is provided with a local bus adapter interconnecting the subsystem with the bus. Busy lines are provided, one for each port on the bus, and all such busy lines are connected to all of the ports for use by any such port when the latter is acting as a source. Each busy line is uniquely connected ...

A loop system couples a CPU channel to bulk storage devices via a loop controller and device adapter. The loop system is characterized by equal fixed-length, multi-byte frames, each frame of which being assignable to only one terminal at a time. The system is further characterized by having a fixed loop delay greatly exceeding the frame duration by virtue of the high data rate. Dynamically variable frame assignment occurs when the primary terminal generates an unassigned empty frame in response ...

An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture of the internal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one w...

An interface circuit for use in a data transmission system has a first port for connection to a 16 wire data highway of the type proposed by the I.E.C. (International Electrochemical Commission) for the interconnection of instruments, and a second port capable of being connected to an eight-wire or two-wire data link. The interface circuit includes an encoding circuit operative to encode at least some commands applied to the first port, and an enabling circuit for selectively enabling data appli...

A hand-shake type control circuit for controlling a data transfer circuit according to the status of a data transfer request signal. The data transfer request signal is initially received at a NAND gate and is also directly coupled to the reset input of are set flip-flop. The output of the NAND gate is used as a first control signal to set the flip-flop and to cause another circuit to activate data transfer. The flip-flop output is a second control signal which is reset only when the transfer re...

Data are asynchronously transferred between a microprocessor and a dynamic memory under the control of a memory controller and a circuit for deriving an internal acknowledgment signal. The internal acknowledgment signal is derived in response to the memory controller deriving a signal indicating that the memory is unavailable at the time a transfer request is derived by the microprocessor or in response to a transfer request derived by the microprocessor. A mask signal is generated in response t...