The present invention discloses apparatus and methods for direct memory access (DMA) having particular application for use in displaying digital images in an animated form on a CRT display. The present invention includes a DMA controller coupled over a bus to a frame buffer. The frame buffer includes one or more bit maps representative of the display. A block of memory within the frame buffer is mapped onto corresponding picture elements (pixels) on the display. The frame buffer continuously sca...

A memory architecture having particular application for use in computer systems employing virtual memory techniques. A processor provides row and column addresses to access data stored in a dynamic random access memory (DRAM). The virtual address supplied by the processor includes high and low order bits. In the present embodiment, the high order bits represent a virtual row address and the low order bits represent a real column address. The virtual row address is applied to a memory management ...

An improved memory organization for use in a computer display system including a display having a plurality of display pixels for defining images that includes: a frame buffer memory having a plurality of memory cells organized into a matrix, said memory comprising first and second maps wherein the contents of the maps correspond to the pixels and define characteristics of the pixels, the maps being defined along X and Z axes of the matric; reading means coupled to the frame buffer memory for se...

The present invention provides an improved arbitrator for use in allocating access to a common resource coupled to a plurality of data processing devices ("agents"). An arbitrator is coupled between the resource and each of the agents, for selectively enabling individual agents to access the resource in accordance with a predetermined priority hierarchy. The arbitrator, in the presently preferred embodiment, receives request signals transmitted by an agent desiring to access the resource and all...

A computer memory architecture is most advantageously used in conjunction with a digital computer, to provide an improved high speed graphics display capability. Data representative of digital images to be displayed is generated and/or manipulated by a display processor and stored within a selected portion of the display processor's main memory. Subsequent modifications to the stored image are effectuated by the display processor reading the data from its main memory, performing appropriate oper...

The present invention provides apparatus and methods which are most advantageously used in conjunction with a computer display system incorporating the use of a Z-buffer to provide three dimensional hidden surface elimination. A buffer memory is provided which is sufficiently large such that each display element (pixel) on the display is represented by a 16-bit Z value. The Z value corresponds to the Z axis depth of the object at the particular point corresponding to the pixel. The buffer compri...

A self configuring memory for a computer system. Memory is distributed between a central processor unit (CPU) memory and expansion memory boards that are selectively insertable into expansion slots of the computer system. The CPU memory board and expansion memory boards each provide signals indicating the respective sizes of the memories. Logic circuitry on each expansion memory board determines the cumulative amount of memory in the system. This value is passed on to an adjacent expansion memor...

A circuit which computes the scan position of any pixel on the display as the sum of the number of scan lines multiplied by the number of pixels per scan line plus the number of pixels on the scan line to the particular position using an adder for a changing portion of the computation and an incrementer for a constant portion of the computation and combining the two of these to produce a result which accomplishes in a relatively economic fashion what would normally require an inordinate number o...

A matrix arithmetic circuit for processing matrix transformation operations includes a random access memory (RAM) for storing a plurality of numbers in Modulo 256 with multiple tap points numbers format. A multiplier multiplies two of the Modulo 256 numbers in RAM to obtain a product. The product is normalized and added to a third Modulo 256 number stored in the RAM to obtain a result. The result is stored in the RAM and coupled to the data processing system for use in matrix transformation oper...

A method and apparatus which provides for the real time comparison of raster data. The raster data is stored in memory such that raster data corresponding to a specific X-Y coordinate location is consistently written to the same memory location. During the process of storing the data in memory, the data currently stored in the memory is read and compared to the data to be written into the same location in memory. If the data is not the same, the discrepancy and location of the discrepancy is not...