Memory circuits that concatenate multiple FIFOs in parallel to increase the overall depth of the memory circuits. Asymmetric input and output ports can be provided by including a deserializer on the write interface of the memory circuit and/or a serializer on the read interface of the memory circuit. The deserializer disperses the data evenly across all FIFOs, minimizing the write-to-read latency. In some embodiments, at most two of the FIFOs are active at any given time, one being written and o...

Safe mode operation for portable devices supporting multiple protocols includes a portable device that supports multiple protocols, such as a base functionality protocol and an enhanced functionality protocol, reporting to a host device that the portable device supports only a single protocol (e.g., the base functionality protocol). This single protocol will be used for subsequent communication between the host device and the portable device. This reporting to the host device that the portable d...

A method for automatically determining a configuration of an I/O connector panel is disclosed. The method comprises the steps of providing information about the capabilities of the connector card to a memory within the connector card, examining the information in the memory. The method further includes downloading at least one driver to a system coupled to the I/O connector panel based upon the examined information.

Method and apparatus for communication within a programmable logic device using serial transceivers is described. In an example, an integrated circuit includes a first module and a second module. The first module and the second module each include a transceiver coupled to a serial/parallel interface, with each transceiver configured with at least one signal conductor for serial communication between the first module and the second module. The first module and the second module are configured to ...

Embodiments of the present invention provide a processor having an inactive state of operation and methods thereof. The processor, according to some demonstrative embodiments of the invention, the processor may include a controller to determine an inactive state of operation is to be entered, and to cause a predetermined set of one or more execution units to execute a predetermined sequence of one or more micro-operations prior to entering the inactive state. Other embodiments are described and ...

The present invention employs two unique identification files associated with the same dual-interface display monitor. Each identification file identifies one of the display monitor's two interfaces, so that each identification file identifies the display monitor as a separate display monitor, with a unique product code and its associated characteristics, to the computer system. When an initiating event occurs, such as a power on self test, hot plug-in, or reboot, the monitor responds to a reque...

The invention illustrates a system and method of sharing content with multiple peer device while protecting the content from unauthorized use. In one embodiment, the system and method comprises: identifying a plurality of peer devices within a predetermined area wherein each of the plurality of peer devices includes an interface framework; directly transmitting content among the plurality of devices; and a selected plurality of peer devices requesting a license from a digital rights management s...

A method and apparatus for providing computer code updates through an integrated circuit card (smart card) interface. The smart card interface within a computer control device determines whether the card that is inserted into the smart card interface is either a memory card or a conventional smart card. Once the smart card interface has detected that the memory card has been inserted, the interface requests data from the card. The interface provides the computer code to the memory of the compute...

A method for using a personal computer memory card international association (PCMCIA) controller to communicate with an Integrated Drive Electronics (IDE) drive which includes performing a transfer between the static random access memory (SRAM) controller and the IDE drive using PCMCIA interface signals to communicate with the IDE drive and a general purpose input/output signal to communicate with an interrupt request of the IDE drive.

A playback apparatus including a playback unit which plays back audio information and the like, an accommodation unit which accommodates a detachable recording medium, and a controller. The controller causes the playback unit to access to the recording medium through the accommodation unit according to a first communication standard (PCMCIA) and causes an external apparatus to access to the recording medium according to a second communication standard (ATA) different from the first communication...