A tester for the collision detector of a transceiver for a multiple access data communications network using carrier-sense collision detection for controlling access to the network. A squelch circuit is employed in the transceiver's transmitter for enabling and disabling the transmitter output. An end-of-transmission detector monitors the squelch circuit to detect the termination of a transmission. Upon termination of a transmission, a collision simulator circuit supplies to the transceiver's re...

A signal level detecting circuit comprises an input terminal to which an input signal with level variations is applied, a level comparator operative to compare the level of the input signal with the level of a reference signal variable in level and to produce a comparison output signal having first and second levels in response to differences between the level of the input signal and the level of the reference signal, a control signal generator operative to produce control signals one of which i...

A motion detector in which an oscillator-detector transmits a series of narrow bursts of radio frequency, electromagnetic energy, the period of which varies as a function of the radial motion of the object relative to the detector, and the varying pulse frequency provides information that an object is moving radially. Such a detector in which the varying pulse frequency of the oscillator-detector is converted to a varying D.C. voltage the magnitude of which varies at a rate determined by the rat...

1. A track detection system comprising; receiving means for receiving refted radio frequency signals from an object in a given medium, range storage means operatively coupled to said receiving means for storing range, information therein between a minimum and maximum range, position indicating means operatively coupled to said receiving means for indicating the direction from which said radio freuqency signals are received, position storage means comprising shift register means operatively coupl...

A detector circuit utilizing two comparators, the first of which initially switches output at a first bias level, and the second of which switches output responsive to a preselected voltage on a capacitor. The voltage on the capacitor is controlled by the output of the first comparator which charges and discharges it through a dual time constant arrangement in order to sensitize the detector to activate a recorder after a preselected delay only upon receipt of a particularly shaped long duty cyc...

Apparatus and method for testing surface defect on an object are disclosed, which comprise an illumination means for illuminating collimated lights onto a surface of the object obliquely to the surface and from two symmetrical directions, a sensor composed of a TV camera or a linear image sensor for sensing diffused reflected lights from the surface of the object in the direction perpendicular to the surface, a classification means for discriminating the sensed image signal by a threshold level ...

A sync detect circuit for detecting a sync code in a stream of digital data includes a counter that converts locally generated clock pulses to a plurality of discrete addresses that occur every bit period of time. The addresses are applied to a PROM which upon being addressed provides a sync verify code. The sync verify code is applied to a sync verify detector which provides an enable signal to the address generator if the code compares with the logic levels of a coincident bit in the stream of...

A circuit for use on an integrated circuit chip for detecting the operative connection of a crystal used to control an on-chip crystal controlled oscillator, which generates a cyclical clock signal, by detecting the presence or absence, respectively, of the cyclical clock signal and for providing an output control signal in response thereto to an on-chip terminal pad control circuit which automatically enables an on-chip terminal pad to be utilized as a clock signal output terminal pad if the cy...

Readily available digital logical circuit components are arranged in circuitry for enhancing demodulation of frequency shifted or phase shifted modulation signals in the presence of a received carrier wave and inhibiting demodulation in the absence of any recognized carrier wave. The circuitry is arranged for measuring the time between adjacent impulses as received including noise impulses which penetrate an input band-pass filter. The preponderance of signal impulses lie within predeterminable ...

A master station communicates with remote stations by respective transmit-receive pairs. Quadra-phase modulation is utilized, involving a carrier having two characteristic frequencies not present during bursts of a communicated signal, which bursts are known to last for a fixed duration. Signals on a receive pair are detected, and phase locked loops are tuned to the characteristic frequencies of the carrier and produce logical signals to indicate whether the characteristic frequencies are presen...