A digital-to-digital converter is arranged to provide "decimated" output samples at rate f.sub.0, each of which represent a group of input samples received at a rate m times greater. Each output is generated using overlapped triangularly weighted accumulation on an interval including 2m preceding input samples. The samples near the beginning and end of each accumulation interval receive the smallest weight, and the samples at the middle of the interval receive the greatest weight. The converter ...

The present invention relates to a digital-to-digital code converter, or decimator, which implements sinc.sup.3 processing. The input signal (X) to the code converter comprises a series of groups, each group including a series of N digital sample values occurring at high rate (1/.tau.) which are converted within the converter, using sinc.sup.3 processing, into a single digital value occurring at, for example, a (1/N).tau. rate for delivery to the converter output (Y). The code converter comprise...

A digital modulator and digital demodulator with quadrature amplitude modulation (QAM) schemes, which are designed to modulate or demodulate RZ-coded baseband signals. The digital modulator comprises first to fourth roll-off filters and a first and second inverters connected to the second and fourth roll-off filters. It also comprises a parallel-to-serial converter to successively selects the outputs of the first roll-off filter, third roll-off filter, first inverter, and second inverter. A D/A ...

A system controller 115 has a function of changing the position and the orientation of character data to be superimposed on the image data, in accordance with the operation of one of orientation keys. Specifically, when a downward key has been pushed, the character data is superimposed on a lower portion of the image data, not revolved and but oriented upward. When a rightward key has been pushed, the character data is revolved counterclockwise through 90 degrees, and is located along the right-...

A digital modulator and digital demodulator with quadrature amplitude modulation (QAM) schemes, which are designed to modulate or demodulate RZ-coded baseband signals. The digital modulator comprises first to fourth roll-off filters and a first and second inverters connected to the second and fourth roll-off filters. It also comprises a parallel-to-serial converter to successively selects the outputs of the first roll-off filter, third roll-off filter, first inverter, and second inverter. A D/A ...

An improved filter technique, as for example, for use with ladder digital filters which allows any LC-ladder filter to be simply translated into a corresponding digital structure. If one of the characteristics of an adaptor is chosen equal to unity, the output of that adaptor will be independent of the input which means that the direct path between the input and output is interrupted, thus eliminating undesirable closed loops to exist. The invention also provides for isolation between input and ...

The invention concerns a digital coder subject to a compression law having multiple linear segments with slopes decreasing in geometrical progression having a ratio of 1/2, in which a chain of threshold detectors in a linear progression is used a first time to determine the number of the segment, then a second time to determine the position of the level on the segment.

A digital circuit has a memory circuit and a logical circuit connected in cascade between first and second delay circuits. The first delay circuit controls an input signal to the digital circuit, so that the delay of the input signal due to a stage or stages preceding to the digital circuit may fall within a delay by the first delay circuit, and the second delay circuit controls an output signal from the digital circuit, so that delays due to the memory and logical circuits may fall within a del...

A digital filter for a plural digitally expressed pulse code modulated (PCM) signal utilizes a storage register to retain several samples of the signal and obviates the need for digital multiplication circuits by using a delta coding for the filter coefficients. Processing steps are at a multiple of the sampling rate and at each step, the value of one stored sample is combined additively or subtractively with previously stored sample values as determined by stored delta coefficient values. The s...

A digital transducer comprises a container having two disparate materials therein defining an interface, the interface being movable through the container responsive to a force, or forces, applied to one, or both, of the materials. A plurality of sensors are spaced along the container for sensing the interface, each of which is responsive to the presence of one of the materials. Means are included for suppressing the outputs of all of the sensing means responsive to the one material except that ...