A circuit adapted to a first-in/first-out device (“FIFO”) is disclosed. The circuit includes a counter and a first end of packet detector that is coupled to the counter. The first end of packet detector increments the counter if an end of packet is detected at an input of the FIFO. The circuit also includes a second end of packet detector coupled to the counter. The second end of packet detector decrements the counter if an end of packet is detected at an output of the FIFO. A detector circuit i…

A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.

A method for computing a decimation-in-time Fast Fourier Transform of a sample is provided, the method including inputting first 2B-bit values representing the sample into a radix-4 first section of the decimation-in-time Fast Fourier Transform and performing first complex 2B-bit integer additions and subtractions on the first 2B-bit values to form second 2B-bit values, without performing a multiplication. The method also includes rounding the second 2B-bit values to form B-bit values output fro…

A compact mechanical toy is provided. The toy is a multi-sided game including multiple sides and a plurality of moveable pieces. The toy includes a first part including one side having a cavity shaped to fit any one of the plurality moveable pieces at one time. The toy further includes a second part rotatably coupled to the first part, the second part including a complex cavity in each of the multiple sides, the complex cavity shaped to fit each of the plurality of moveable pieces in a certain o…

A repeater that prevents a node involved in a collision from detecting that the collision occurred, and transmits the data packet received from that node to all other nodes connected to the repeater. The repeater accomplishes this by repeating the data packet received from that node during the collision, and discarding the data packets received from other nodes, thereby allowing a valid data packet to traverse the repeater and all communication medium segments attached thereto. The repeater main…

An apparatus for use in a computer system comprises a first storage area and a circuit, coupled to the first storage area, configured to perform a comparison of a data element A with a data element B. In response to a single instruction, the circuit performs the comparison and outputs a condition field of at least one bits when the comparison of A and B is TRUE, or else the circuit outputs the ones-complement of the condition field when the comparison of A and B is FALSE. The circuit may be used…

A symmetric multiprocessor system constructed from industry standard commodity components together with an advanced dual-ported memory controller. The multiprocessor system comprises a processor bus; up to four Intel Pentium.RTM. Pro processors connected to the processor bus; an I/O bus; a system memory; and a dual-ported memory controller connected to the system memory, the dual ported memory controller having a first port connected to the processor bus to manage processor to system memory tran…

A video recording and playback device (10) incorporates a processor (114) for processing the video signal to detect the presence of commercial messages. Video and audio event detectors (102, 104) detect the presence of events in the signal as it is recorded. The timing relationship of the detected events is analyzed to classify the video segments between events as program material or as commercial messages. After a program is recorded, control marks are generated (132) to indicate the beginning …

An apparatus for adjusting phase relation of a plurality of clock signals in a processor. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates a first output based on a phase relation between those clock signals. A controller then adjusts the delay of the clock signals based on the first output of the phase detection circuit and a bit of a delay shift register to synchronize the clock signals within a predefined range. The controller generates…

A parallel decompressor capable of concurrently generating in parallel multiple portions of a deterministic partially specified data vector is disclosed. The parallel decompressor is also capable of functioning as a PRPG for generating pseudo-random data vectors. The parallel decompressor is suitable for incorporation into BIST circuitry of ICs. For BIST circuitry with multiple scan chains, the parallel decompressor may be incorporated without requiring additional flip-flops (beyond those presen…