A function interface system for use with a fast pattern processor having an internal function bus and an external function bus and a method of operating the same. In one embodiment, the function interface system includes a controller arbitration subsystem configured to process an issued function request received from at least one of the internal function bus and the external function bus and a dispatch subsystem configured to retrieve the issued function request and dispatch the issued function request to at least one associated co-processor via the controller arbitration subsystem.
CROSS-REFERENCE TO PROVISIONAL APPLICATION
This application claims the benefit of U.S. Provisional Application No. 60/186,424 entitled “FPP” to David Sonnier, et al., filed on Mar. 2, 2000, and of U.S. Provisional Application No. 60/186,516 entitled “RSP” to David Sonnier, et al., filed on Mar. 2, 2000, which is commonly assigned with the present invention and incorporated herein by reference as if reproduced herein in its entirety.
CROSS-REFERENCE TO RELATED APPLICATIONS
TABLE-US-00001 Reference No. Title Inventor Date SN 09/798,472 A Virtual Reassembly Bennett, Filed Mar. 2, (BENNETT System And Method of et al. 2001 5-6-2-3-10-3) Operation Thereof SN 09/798,479 A Checksum Engine And David A. Filed Mar. 2, (BROWN 2) Method of Operation Brown 2001 Thereof
The above-listed applications are commonly assigned co-pending with the present invention and are incorporated herein by reference as if reproduced herein in their entirety.
A fast pattern processor having an internal function bus and an external function bus. In one embodiment, a fast pattern processor includes: (1) an internal function bus, (2) an external function bus, (3) a context memory having a block buffer and a argument signature register wherein the block buffer includes processing blocks associated with a protocol data unit (PDU), (4) a pattern processing engine, associated with the context memory, that performs pattern matching and (5) a function interface system having (5A) a controller arbitration subsystem and (5B) a dispatch subsystem.
